The invention relates generally to CMOS-implementable image sensors suitable for three-dimensional applications including time-of-flight (TOF) and phase-based TOF range or depth systems. More specifically, the invention is directed to reducing inter-gate capacitance in such sensors, and enhancing modulation contrast.
It is useful at this juncture to briefly describe TOF systems that can benefit from the present invention. FIGS. 1A-1C depict a phase-based TOF system 100 such as described in U.S. Pat. No. 7,352,454 (2008) entitled Methods and Systems for Improved Charge Management for Three-Dimensional and Color Sensing. The '454 patent is assigned to Canesta, Inc. of Sunnyvale, Calif. and is incorporated herein by reference. TOF system 100 such as described in the '454 patent is phase-based and acquires depth distance Z by examining relative phase (Φ) shift between TOF system transmitted optical energy signals S1, and a fraction of such signals S2 reflected from a target object 20 distance z away.
System 100 includes a CMOS fabricatable IC 110 whereon is formed a two-dimensional array 130 of pixel detectors 140, each of which has circuitry 150 for processing detection charge output by the associated detector. IC 110 also includes a microprocessor or microcontroller unit 160, memory 170 (which preferably includes random access memory or RAM and read-only memory or ROM), a high speed distributable clock 180, and various computing and input/output (I/O) circuitry 190. Among other functions, microprocessor or controller unit 160 may perform distance to object and object velocity calculations. IC 100 further includes an oscillator 115 that is controllable by microprocessor 160 and coupled to optical energy emitter 120. Emitter 120 may be a laser diode or LED, with output wavelength of perhaps 800 nm to 850 nm. Emitter 120 may be allow peak power unit whose output is a periodic signal with perhaps 200 mW peak power, and a repetition rate of perhaps 100 MHz. For ease of illustration assume that the emitter output, which may be transmitted through optical system 125 may be represented as A·cos(ωt), where waveform period T is given by T=2π/ω. It is understood that S1 may be other than sinusoidal, e.g., perhaps square wave, triangular wave, among other waveforms.
As shown by FIGS. 1B and 1C, there will be a phase shift Φ due to the time-of-flight (TOF) required for energy transmitted by emitter 120 (S1=cos(ωt) to traverse distance z to target object 20, and be reflected as return energy S2=A·cos(ωt+Φ), where coefficient A may represent brightness of S2. The S2 return energy is detected by a photodetector 140 in array 130, where the array may include perhaps 100×100 or more photodetectors. The phase shift Φ due to time-of-flight is:Φ=2·ω·z/C=2·(2πf)·z/C 
where C is the speed of light 300,000 Km/sec. Thus, distance z from energy emitter (and from detector array) to the target object is given by:z=Φ·C/2ω=Φ·C/{2·(2πf)}
In system 100, phase Φ and distance z preferably are determined by mixing (or homodyning) the signal S2=A·cos(ωt+Φ) detected by each pixel detector 140 with the signal driving the optical energy emitter S1=cos(ωt). Mixing resulted from differentially modulating the quantum efficiency of the photodetectors in the array. Different banks of photodetectors 140 in sensor array 130 may be quantum efficiency modulated at different phase shifts, e.g., 0°, 90°, 180°, 270°. The signal mixing product S1·S2 will be 0.5·A·{cos(2ωt+Φ)+cos(Φ)} and will have a time average value of 0.5·A·cos(Φ). The system output, denoted DATA, can include depth images as well as other acquired information. System 100 requires no moving parts, can be implemented in CMOS, is operable with or without ambient light, and can have many applications including implementing virtual input devices, range finding, gesture recognition systems, object recognition, etc.
Understandably, acquiring accurate depth images will depend upon the nature and quality of the pixel sensors, and their ability to accurately and correctly collect charge generated by incoming optical energy. As described herein, the present invention enables detectors 140 in array 130 to maximize collection of charge useful to creating an accurate depth image, and to minimize collection of charge that would detract from creating an accurate depth image of the rate of collection in the elongated direction.
It is useful to review challenges associated with efficient collection of photon-energy induced charge in a semiconductor substrate to gain a fuller appreciation of the present invention. The '454 patent provides a useful starting point, and will be described briefly with respect to FIGS. 2A-2E, and FIGS. 3A-3B. As more fully described in the '454 patent, preferably detectors 140 collected charge in two stages. The detector structure included multiple finger-shaped poly material gates, denoted A-gates and B-gates, disposed parallel to each other along a y-axis, and spaced-apart a distance much shorter than their length along an x-axis. Elongated charge barrier regions were formed intermediate adjacent A-gates and B-gates to minimize the collection effects of A-gates upon B-gates and vice versa, and thus avoid inter-gate transfer of charge being collected. Detection-generated charge first moved laterally in the X-direction toward a gate biased at a high clock potential at the time. The charge (electrons) only needed to travel locally and the δX distance between adjacent elongated gates was small and the electric field intense. Thereafter the charge moved laterally at a slower rate along the length of the finger-shaped gates for final collection and readout.
FIG. 2B depicts a detector 140, based upon embodiments of the 454 patent. Elongated gates G-A and G-B are coupled to receive G-A and G-B bias clock signals that can be synchronously generated, with respect to phase and frequency, from a master clock generator, e.g., 180, which master clock generator also controls TOF system 100 optical energy emitter 120 (see FIG. 1A). As such, frequency of the G-A and G-B bias clock signals need not be identical to frequency of the master clock generator, but they will be synchronously related. Similarly, phase of the G-A and G-B bias clock signals will be synchronously related to the master clock generator signal. One could, of course, use separate generators for each (or some) of these signals if the proper signal relationships were maintained. FIG. 2B is a cross-section of a sensor detector structure 140-1, with a plot of surface potential at the silicon-gate oxide interface versus position along the X-direction. As noted, charge transfer collection gates A (G-A) and charge transfer collection gates B (G-B) preferably are interleaved elongated or finger-shaped gate structures 620. The nomenclature gate A and gate G-A, gate B, and gate B-G may be used interchangeably, and descriptions of gate G-A are applicable to gate G-B, and vice versa. Two magnitudes of gate A potential are shown, 2.0 V and 3.3 V, with a constant 0 V gate B potential. For 2.0 V gate A potential, surface potential is drawn with solid lines, and. is a somewhat idealized profile with relatively little potential migration left and right along the X-axis relative to location of the A gates G-A. Phantom lines are used to depict the 3.3 V gate G-A potential profile. With respect to the detectors shown in FIGS. 2A-2E, when gate potential VA is high, gate potential VB is low and vice versa. Depending upon the high or low state of gate potentials VA or VB, ideally substantially all charge would be collected by gates G-A (when VA=high, VB=low) or gates G-B (when VB=high, VA=low).
In FIG. 2A, consider the case of 2.0 V potential for gate G-A: Under this bias condition, charge-generated electrons under the gate G-B region are trapped. (The trapped electrons are depicted as encircled minus signs.) Trapping occurs because escape from this region requires the electrons to first overcome the potential barrier represented by solid line profile representing the 2 V bias. For the trapped electrons to migrate left or right in FIG. 2A requires overcoming regions of increasing negative potential, e.g., the solid line profile becomes more negative in the left or right direction. But this negative potential tends to repel the electrons, which remain trapped beneath the gate G-B region, as shown. A potential barrier as low as perhaps 100 mV will be sufficient to prevent electron migration as the thermal energy associated with the trapped electrons is insufficient to overcome this barrier. As a result, the electrons will remain trapped beneath the G-B regions, as shown in FIG. 2A.
The term modulation contrast (MC) denotes a measure of charge arrival time categorization efficiency, and does not refer to dark or light contrast of an image that may be acquired by Canesta, Inc. sensors or systems. High modulation contrast is desired for high performance sensor applications. But in a high modulation contrast application, it is desired to elevate gate potential G-A to a higherlevel, e.g., to 3.3 V rather than 2.0 V. But elevating gate potential G-A to 3.3 V causes the potential profile to take on the appearance represented in FIG. 2A by the phantom lines. Unfortunately the resultant potential barrier is insufficient to keep charge-generated electrons associated with (or trapped beneath) gate G-B from being attracted to gate G-A. Looking at the phantom line potential profile in FIG. 2A, migration of the trapped electrons laterally no longer requires Overcoming an increasingly negative potential profile; the profile is in fact increasingly positive, a condition favorable to movement of electrons. As a result, charge-generated electrons associated with gate G-B cannot be held (or trapped) in that region and will migrate to gate region G-A. An undesired result is that effective charge collection is impaired, and detector performance is degraded, which is to say modulation contrast decreases. Various factors affecting modulation contrast (MC) are described in the '454 patent. Generally modulation contrast has a maximum value of four (400%), with two or 200% being a more realizable value in actual TOF systems.
Note in the above example that the barrier that existed when gate potentials G-A=2.0 V and G-B=0 V disappeared when gate potential G-A was raised to 3.3 V. Conversely the voltage barrier that may exist at gate potentials G-A=3.3 V and G-B=1.0V will disappear when gate potential G-B is lowered to 0 V. One aspect of the '454 invention was directed to maintaining a potential barrier when the high magnitude of the gate potential is increased or the low magnitude of the gate potential is decreased. Operation of the detector system at these upper and lower extremes of gate potential is desirable in that detector performance is enhanced.
In the embodiment of the cross-sectional view shown in FIG. 2B, a sensor detector structure 140-1 is provided with implanted regions 600 that act as potential barriers. If one could see these implanted regions from the top of the detector substrate, they would appear to be longitudinal or finger-shaped, parallel and interleaved between adjacent finger-shaped polysilicon gates G-A, G-B. These potential barriers reduce migration of charge-generated electrons between adjacent finger-shaped gates, e.g., from G-A to G-B and vice versa. In the embodiment shown, structure 140-1 includes finger-shaped p+ doped regions 600 that act as an voltage barrier to undesired charge migration, even in the presence of large (e.g., 3.3 V) G-A gate potential. Further, barriers 600 advantageously reduce dark current that would be associated with other types of isolation barriers, e.g., shallow trench isolation, although in some applications shallow trench isolation may in fact be used.
Note in FIG. 2B that even at relatively high 3.3 V G-A gate potential and relatively low G-B gate potential, the presence of p+ regions 600 deepens the potential barrier between the interleaved finger-shaped G-A and G-B gate regions. The presence of the potential barrier advantageously enables detection-generated electron charge collected by gate G-B to remain trapped generally beneath the G-B region for a sufficiently long time to be collected, e.g., for a period of perhaps 100 μs to perhaps as long as a few ms. The charges trapped generally beneath the G-B region repel each other. This mutual repulsion results in the charges being collected at respective charge collection regions (see collector region 630, FIG. 2C) in the detector structure without any gate-induced horizontal electric field.
Advantageously, p+ doped implant regions 600 may be fabricated without need for critically controlled parameters such as magnitude of implant dosage and/or implant depth into substrate 110 of structure 140-1. Masking and doping steps used to create regions 600 may be shared with existing doping steps used elsewhere to fabricate overall structure 140-1.
As will now be described with reference to FIG. 2C, detection problems arise if charge ultimately collected at collection region 630 is drawn out by too high a gate potential at finger-shaped gate regions 620. FIG. 2C depicts structure 140-1 cut along a preferably polysilicon finger-shaped G-A gate 620. It is understood that if gate G-A potential (drawn in phantom line) is too high, a substantial number of electrons (shown as encircled minus signs) can be drawn out of n+ collection region 630 and into the region beneath gate G-A. In FIG. 2C, the G-A potential becomes more positive in the direction of G-A relative to region 630, which potential attracts the negatively charged electrons, as suggested by the left-pointing arrow. Electrons so drawn from the desired collection region into the G-A region may overwhelm the otherwise correct detection function of structure 140-1, as many of these electrons may be lost to G-B gate collection regions. What is needed here is a mechanism to prevent high G-A gate potential from drawing out charge collected in n+ collection region 630. Such a mechanism is provided in the embodiment of FIG. 2D, namely bias gate 640.
Turning now to FIG. 2D, a bias gate 640 has been added to structure 140-1 in FIG. 2C, to form an improved detector structure 140-1. Improved structure 140-1 reduces or prevents charge loss from the n+ collection regions to the gate regions, even in the presence of relatively high gate potential. In the embodiment of FIG. 2D, a bias potential VN+ of about 2.5 V is coupled to n+ collection region 630, and a bias potential VBG of perhaps 1.5 V is coupled to bias gate 640. The magnitude of bias potential VBG is sufficiently low relative to magnitude of bias potential VN+ such that charges collected in bias gate 640 region will be attracted to the N+ 630 region. At the same time, bias potential VBG is sufficiently high in magnitude such that region G-A collected charges will flow in the bias gate 640 region when the modulation clock signal at gate G-A 620 is low. Preferably spacing of bias gate 640 and polysilicon gate 620 is substantially as small as can be produced by the CMOS fabrication process used to create structure 140-1.
Also shown in FIG. 2D are potentials at the surface of silicon structure 1401. The VN+=2.5 V, V G-A=0 V voltage profile is a potential regime that encourages electrons collected or trapped beneath the G-A region to move to collection source region 630 without encountering a potential barrier. The VN+=2.5 V, V G-A=3.3 V voltage profile is a potential regime in which bias gate 640 provides a potential barrier that advantageously prevents electrons collected in N+ region 630 from being pulled into the region beneath gate G-A. Thus it is seen that providing appropriate VN and VG-A bias potentials to structure 140-1, charge loss can be minimized if not substantially eliminated.
In an alternate embodiment to structure 140-1 shown in FIG. 2D, bias gate 640 may be replaced with a light p doping. The light p doping region will create a potential barrier similar to that created and described above by bias gate 640. In short, such doping has the same effect of creating a potential barrier between gates G-A (respectively G-B) and collection source 630.
Turning now to the plan view of FIG. 2E, the detector structure shown includes bias gates 640, which improves charge collection characteristics. For ease of illustration, FIG. 2E does not depict the p doped barriers, and also depicting physical connections to the individual bias gates 640. Such connections are indicated symbolically as a heavy “wire”, with encircled “x's” indicating electrical connection to the polysilicon associated with elongated or long finger-shaped gates G-A or G-B. Adjacent the distal ends of finger-shaped polysilicon gate structures G-A, G-B beneath the “x” denoted contacts are bias gate 640 and collection source 630.
Note that electrons collected by a source region 630 need not be captured by gate G-A (or G-B) during a common modulation cycle of G-A (or G-B) clock signal voltage. Such electrons might have been captured by a gate a period of time ago perhaps on the order of many microseconds (μs) or perhaps milliseconds (ms). Such electrons can linger in the substrate region beneath a gate for such lengths of time until ultimately being captured by an adjacent collection source region 630. According to some embodiments of the present invention, such electrons are induced to cross over to bias gate 640 as a result of two actions: the presence of relatively larger numbers of electrons accumulated under gate regions, and the repulsion effect between these electrons. The '454 patent describes various techniques to optimize the detector geometry including use of “T”-shaped gates G-A, G-B to enhance charge collection to increase length of the interface area between G-A (or G-B) gate regions, and bias gate 640. Techniques to reduce source capacitance and various masking techniques were also described.
Consider now FIGS. 3A-3B, taken from the '454 patent, where incoming optical energy is shown as zig-zag lines. FIGS. 3A and 3B are a cross-section of a sensor structure 240″-1, which may be used as sensor-detectors 140 in FIG. 1A, for collection of non-polycided gates at a high potential of 3.3 V. Within silicon substrate 410, field lines terminate on a gate G-A or on a gate G-B. In FIG. 3A gates G-A are at a high potential, perhaps 3.3V and gates G-B are at a low potential, perhaps 0V. In FIGS. 3A and 3B, the collection regions 480 for each of the two types of gates is shown pictorially in gray. The p+ barriers that were present in the structure of FIG. 2B are not shown in FIGS. 3A and 3B. As seen in FIG. 3A, gates G-A at the higher potential have larger collection areas. In practice the collection areas for G-A occupy substantially the entire area not occupied by the collection areas for gates G-B, however for ease of illustration, these enlarged collection area are depicted as regions confined to underneath gates G-A. Note that increasing magnitude of the gate potential of G-A increases the volume of these collection regions. It will be appreciated that the larger the collection region of gate G-A becomes, the smaller will become the collection region of gates G-B which, which are biased low at perhaps 0 V in FIG. 3A. This is because the volume of the collection regions for gates G-A compete for collection volume with the collection regions of gates G-B, which effective are compacted as the collection regions of gates G-A increase.
It is difficult to decrease the collection regions of gates G-B by lowering voltage magnitude of VB coupled to G-B. This is because decreasing VB to too low a level may cause gates G-B to lose already collected charges, a regime of operation that is to be avoided. However increasing the VA voltages on gates G-A reduces the collection regions of gates G-B in a more controlled fashion, and is a preferred manner of increasing the ratio of the collection region of gates G-A to the collection region of gates G-B, when VA is high, and VB is low. This increase in the ratio advantageously increases modulation contrast, and hence performance of the TOF system. High modulation contrast is always desired and embodiments of the '454 patent achieved high modulation contrast, using standard 0 V to 3.3 V swings common for 0.18 um devices. As will be described later herein, embodiments of the present invention achieve high modulation contrast, but advantageously using lower voltage swings. FIG. 3B is similar to FIG. 3A but depicts the complementary case when VB is high potential, perhaps 3.3 V, and thus collection regions 480 generally beneath gates G-B are large, and VA is at low potential, e.g., about 0 V, and collection regions beneath gates G-A are small.
In forming detector structures as described earlier herein, it is preferred that if a lightly doped p substrate 110 is used (dopant concentration of about 5·1014/cm3) then a spaced-apart distance between adjacent finger-shaped gates G-A, G-B of about 0.5 μm to 2 μm can be realized. Following fabrication, suitable bias voltages for the n+ regions, high and low magnitudes for G-A and G-B clock voltages, and bias gate potentials will be determined. Desired operating voltages may be determined by sweeping these potentials and comparing relative detector performance for all swept operating points, and maintaining the best bias regime configurations. It is preferred that a relatively thick oxide on the order of 50 Å be employed to protect gate oxides from damage due to high gate potentials, including potential magnitudes not likely to be encountered in normal substrate operation. While various embodiments of the present invention have been described with respect to a p substrate 110, it is understood that an n substrate could instead be used, or even an n well or a p well, providing doping levels are acceptable low for all modulation regimes.
Thus in CMOS detectors useable with TOF systems, there is a need for a detector structure that collects charge efficiently maintains or preferably enhances high modulation contrast, and can achieve these goals with relatively low voltage transitions. Further there is a need for a detector structure with reduced inter-gate capacitance.
The present invention provides CMOS detectors having (especially short collection time detectors) with a mechanism to manage and maximize collection of useful photocharge, while minimizing collection of not useful late arriving charge. The overall result is to enhance accuracy of depth data acquired by TOF systems.